PCS

 

• HI-BER: high bit error rate of sync header

• LOA: Loss of Alignment marker

• LOBL: Loss of block lock

• Invalid Sync header: first 2 bits of the 64/66 block header

• Invalid alignment marker: inserted every 16383 block on each virtual lane it contains the Virtual lane identifier

• BIP: generates Bit Interleave Parity Error

 

Tap on View PCS Lane Details to see additional details such as PCS # and VL ID for each alarm/error. The magnifying glass displays Count and Rate error details.

 

BERT Results- PCS

 

BERT Results - PCS Lane Details